Recent years have seen progress in the research and development of variable resistance nonvolatile memory devices (hereinafter also referred to as nonvolatile memory devices) having memory cells which include variable resistance nonvolatile memory elements (hereinafter also referred to as variable resistance elements) as nonvolatile memory devices capable of high-speed operations and suitable for large-capacity storage. Here, a variable resistance element is an element whose resistance value reversibly changes based on an electric signal and, furthermore, is an element that is capable of storing data corresponding to a resistance value in a nonvolatile manner.
A known nonvolatile memory device using variable resistance elements includes an array of memory cells known as 1T1R memory cells organized in a matrix. Each 1T1R memory cell is provided in the vicinity of a cross-point of a bit line and a word line arranged orthogonal to each other and includes a transistor and a variable resistance element connected in series. In a 1T1R memory cell, one terminal of a two-terminal variable resistance element is connected to a bit line or a source line, and the other terminal is connected to the drain or the source of the transistor. The gate of the transistor is connected to a word line. The other terminal of the transistor is connected to a source line that is not connected to the one terminal of the variable resistance element or a bit line. The source line is arranged parallel to the bit line or word line.
Moreover, a known nonvolatile memory device having a different memory cell structure includes an array of cross-point memory cells known as 1D1R memory cells organized in a matrix. Each 1D1R memory cell is provided at a cross-point of a bit line and a word line arranged orthogonal to each other and includes a diode and a variable resistance element connected in series.
Hereinafter, a typical conventional variable resistance element will be described (Patent Literature (PTL) 1).
PTL 1 discloses a variable resistance element including ion conductive variable resistance elements, each of which comprises an insulating film (specifically amorphous Gd2O3) and a conductive film (specifically CuTe).
FIG. 14 is a schematic diagram of a cross section of the variable resistance element disclosed by PTL 1. A variable resistant element 5 includes a stacked structure of two electrodes 1 and 2 and a conductive film 3 and insulative film 4 interposed between the two electrodes 1 and 2. Here, a metal film, an alloy film (a CuTe alloy film, for example), or a metallic compound film comprising one or more metal element selected from Cu, Ag, Zn are disclosed as examples of material used for the conductive film 3. Moreover, an insulator such as amorphous Gd2O3 or SiO2 is disclosed as material for the insulative film 4.
Next, writing to the variable resistance element 5 shown in FIG. 14 will be described. When a voltage that causes the potential of the electrode 1 to exceed the potential of the electrode 2 is applied to the variable resistance element 5, ions of the metal are pulled toward the electrode 2 and enter the insulative film 4. When the ions of the metal reach the electrode 2, the upper and lower electrode 1 and electrode 2 become conductive, resulting in a low resistance state (LR writing). In this way, data is written into the variable resistance element 5 (LR writing). Conversely, when a voltage that causes the potential of the electrode 1 to be less than the potential of the electrode 2 is applied, ions of the metal are attracted to the electrode 1 and exit the insulative film 4. As a result, insulation properties across the upper and lower electrode 1 and electrode 2 increase, resulting in a high resistance state (HR writing). In this way, data is erased from the variable resistance element 5 (HR writing).
FIG. 15A and FIG. 15B show the waveforms of voltage pulses applied to the variable resistance element 5 when data recording is performed once.
FIG. 15A shows the waveform of a pulse when writing is performed (storing of data “1”). Here, first an erase voltage pulse PE is applied as a reverse polarity voltage pulse, and then a normal polarity PW voltage pulse corresponding to the data to be stored is applied. In other words, a voltage pulse P1 for storing the data “1” includes a set of two voltage pulses, PE and PW.
FIG. 15B shows the waveform of a pulse when erasing is performed (storing of data“0”). Here, first a write voltage pulse PW is applied as a reverse polarity voltage pulse, and then a normal polarity PE voltage pulse corresponding to the data to be stored is applied. In other words, a voltage pulse P0 which stores the data “0” includes a set of two voltage pulses, PW and PE.
Storing data in the variable resistance element 5 using the voltage pulses P1 and P0 shown in FIG. 15A and FIG. 15B limits the number of times the voltage pulse PW or PE of the same polarity are consecutively applied is limited to two or less. With this, it is possible to control a change of a resistance value of the variable resistance element 5 (an increase of a resistance value from LR state or a decrease of a resistance value from HR state) which is caused by successive application of the voltage pulse PW or PE having the same polarity many times, thereby extending rewrite life.